. calcomp :: H-84-0045B vistagraphic DR11W DR11B DR11C and DR11B parallel interface users manual Nov1984 . n BUSY goes false. The 24 bit SPI generates ODR (Data Received) and resets OCTL. IF READY is still reset, (indicating a DMA transfer), theparallel interface will generate another CYCLE REQUEST A on thetrailing edge of OCTL; otherwise, the output transfer iscompleted. 24 CL D CL CD< QO CO QZCJCO CL Q o < CO CJcoOq LU CO Ir DQ-h-D o COI o D O(TII- co <Q CO cr CO <C i: O Sr Q X CE jt - UJ^. COOQ K =^ X ^- < ^ Q. LU< CO CC CO QZ X O ^ (J -Z Q- UJ ^ <Q - CO -Q Z LU UJ X,CO
. calcomp :: H-84-0045B vistagraphic DR11W DR11B DR11C and DR11B parallel interface users manual Nov1984 . n BUSY goes false. The 24 bit SPI generates ODR (Data Received) and resets OCTL. IF READY is still reset, (indicating a DMA transfer), theparallel interface will generate another CYCLE REQUEST A on thetrailing edge of OCTL; otherwise, the output transfer iscompleted. 24 CL D CL CD< QO CO QZCJCO CL Q o < CO CJcoOq LU CO Ir DQ-h-D o COI o D O(TII- co <Q CO cr CO <C i: O Sr Q X CE jt - UJ^. COOQ K =^ X ^- < ^ Q. LU< CO CC CO QZ X O ^ (J -Z Q- UJ ^ <Q - CO -Q Z LU UJ X,COH CO nO X^i2 O QZ UJ COUJ Q< CO (J o CEQ o z H- Q CO O Qqi? UJ -ICO H- *^ CO UJ tX ZCO OUJ Q li : O UJO ^ I c~ CL D Q- CO si oS a: Q UJ S 0 UJZ a. < UJ co°=^ H UJ QC CE < <H CO 52 X CL XCO X 2 . CO d UJ CO COCO Q •So- 1 O O o UJ < CO -J u O TA UJ CO CJ G CJ Ql ^ UJ o tr Q S. QO < Q o > CO c -u CJ Output Transfer Handshaking Signals 25 INPUT TRANSFERS (see figure on next page) 1. Initialize System. 2. The Vistagraphic System loads the input data register with thedata to be input to the hosto 3. Vistagraphic sets the IWR (Input Word Request). 4. Depending on the current mode of the SPI: a. If the SPI is not performing any operations (READY = 1 andFNCT2 = 0), the SPI will go directly to step 5. b. If the SPI is performing an output transfer (READY = 0 andFNCTl = 0), the SPI will set the ATTN flip flop; the ATTNsignal to the host DRll will be inhibited until the outputoperation is completed (READY = 1), The SPI will go to step6. c. If the SPI is performing an input transfer (READY 0 andFNCTl = 1), the SPI will go directly to step lOo 5. The leading edge of IWR sets the ATTN line on the parallelinterface, 6e If the Interrupt Enable (IE) has been set on the DRll, the DRllgenerates an interrupt
Size: 1393px × 1793px
Photo credit: © Reading Room 2020 / Alamy / Afripics
License: Licensed
Model Released: No
Keywords: ., bookcentury1900, bookdecade1910, bookidbitsaverscal, bookyear1919
